The present invention relates generally to signal synthesizers and more particularly to frequency synthesizers utilizing fractional-N techniques to provide an output frequency which is related to a reference frequency by a rational divisor N.F where N is an integer portion and F is a fractional portion of the divisor.
A frequency synthesizer is a device which generates an output signal having a frequency which is an exact multiple of a reference frequency, the accuracy of the output signal frequency typically determined by the accuracy and stability of the referenced frequency source. Frequency synthesizers utilizing a phase lock loop (PLL) to provide an output signal having a selectable, precise and stable frequency are well known in the art. Typically a PLL includes a tunable oscillator such as a voltage controlled oscillator (VCO), the output of which is locked to a known reference signal by means of a phase comparator. The phase comparator generates an output voltage or current that is proportional to the phase difference between the known reference signal by means of a phase comparator. The phase comparator generates an output voltage or current that is proportional to the phase difference between the known reference signal and the VCO output signal. The output of the phase comparator is coupled back to the input of the VCO to tune and lock the VCO to a desired frequency. This forces the VCO output to have the same frequency as the reference signal. To provide a frequency synthesizer having a variable output frequency, a divisor circuit is interposed between the output of the VCO and the phase comparator, wherein the VCO output frequency is divided by a selectable divisor before it is compared with the reference frequency. The VCO output frequency will then be an exact multiple of the referenced frequency. If the divisor, N, is an integer, the smallest increment in the VCO output frequency value is necessarily equal to the magnitude of the reference frequency itself. Thus, in order to provide a frequency synthesizer having a small step size between adjacent output frequencies, a very low reference frequency is required. However use of a very low reference frequency introduces unacceptable effects such as limited frequency range and a long settling time for the PLL.
A technique known as fractional-N synthesis is often utilized to synthesize output signals having a frequency which is a rational multiple of the reference signal frequency. Typically, frequency divider circuits are implemented in such a manner that they only divide by an integer value and it is necessary to simulate fractional division by changing the divisor integer value temporarily during the course of a division cycle. The non-integer division ratios are realized by dividing by N+1, for example, instead of N on a proportional number of division cycles to provide an average division ratio which approximates the desired rational divisor number. For example, if the desired rational divisor is taken to be N.1, the divide value will be N for nine division cycles and N+1 for the tenth division cycle. Thus, when averaged over ten cycles the division factor equals N.1 and the VCO output frequency will be N.1 times the reference frequency. Such a fractional-N technique is disclosed in U.S. Pat. No. 3,928,813 issued to Charles A. Kingsford Smith on Dec. 23, 1975.
While such fractional-N dividers are widely used for frequency synthesis, switching between different divisor values results in undesirable phase error or phase "jitter" near the desired carrier frequency. When switching between adjacent integer divide ratios, the average divide ratio is correct, but the instantaneous divide ratio is never correct which results in phase error at the phase detector output. This phase error phase modulates the VCO to generate the spurious signals known as phase jitter. Typically, to alleviate the jitter problem a phase error correctional signal is generated and summed into the PLL. The technique, known as phase interpolation, is limited by the ability to precisely generate the required correction signal. For example, to achieve a reduction in the jitter to -70dBc requires a phase interpolation signal having less than 0.03 percent error. It is extremely difficult to generate a correctional signal having the necessary degree of accuracy and such circuitry is complex and expensive and limits the jitter performance of this fractional-N technique.
U.S. Pat. No. 4,609,881 granted to John N. Wells on Sept. 2, 1986 describes a fractional-N frequency synthesizer wherein the phase noise caused by the step change in divisor value is removed by altering the divisor value in accordance with the terms of a plurality of sequences each of which sums to zero and which represents successive rows in a Pascal's triangle. Each sequence is defined by a number of predetermined delays arranged in a predetermined order. Each predetermined sequence periodically alters the divisor value a predetermined number of times by predetermined values such that resulting phase differences present at the phase comparator sum to zero.